Field Programmable Gate Array (FPGA) architecture comprises a programmable routing structure and an array of configurable logic blocks. The programmable routing matrix comprises means for connecting configurable logic blocks (hereafter referred to as logic blocks) to each other. An FPGA provides a combination of programmable logic and programmable connections to a general-purpose routing structure.
In conventional FPGAs, the Programmable Interconnect Points (PIPs) are turned on by loading appropriate values into configuration memory cells associated with the PIPs, thereby creating paths for routing and establishing the logic performed by the configurable logic blocks. The signals on the routing paths change dynamically as values are being written to and read from flip-flops. A large amount of data is exchanged between logic blocks involving complex arithmetic and logic operations. The general-purpose routing resources are used to implement the interconnects between complex logic blocks. Data between the blocks is routed through the available switch matrix structure in the FPGA.
An existing interface between complex logic blocks in FPGA is an interface between RAM and Digital Signal Processor (DSP) block. In conventional FPGAs the blocks of RAM are generated by configuring programmable parts of the FPGA. When the functionality of RAM is desired by multiple end users, it is economical to dedicate a portion of the chip to this purpose, thus allowing the particular function to be implemented at high density.
Signal processing applications require execution of complex arithmetic and logical operations within the Configurable Logic Blocks. These blocks include multiply and accumulate (MAC) units, memory blocks, multipliers, shift registers, adders.
U.S. Pat. No. 5,933,023 describing the existing structure of RAM blocks embedded in FPGAs, and is illustrated by FIG. 1A. The patent describes a structure in which blocks of RAM are integrated with Configurable Logic Blocks in FPGA. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. The logic blocks of the FPGA can use these routing lines to access portions of RAM. The routing lines allow RAM blocks and arrays of RAM blocks to be configured long, wide, or in between, and allow logic blocks to conveniently access RAM blocks in a remote part of the chip.
The drawback in the above said patent is that it cannot be used to provide an efficient routing structure between complex IP cores, where high rate of data exchange is required.
FIG. 1B is a block diagram of a configurable memory array device 200 in accordance with U.S. Pat. No. 6,104,208, which describes the function specific blocks in detail. The configurable memory array device 200 comprises configurable memory array blocks 202 (202-1 through 202-3) connected to a functional block 204 by way of a signal bus 206. The signal bus 206 carries data and control signals, from the functional block 204 to the configurable memory array blocks (202-1 through 202-3) by using bi-directional signal lines 208-1 through 208-3. The configurable memory array blocks 202-1 through 202-3 respectively connect to external circuitry by way of bi-directional input/output (I/O) lines; 210-1 through 210-3.
The connectivity between the DSP block and the RAM blocks in U.S. Pat. No. 6,104,208 is not efficient and the connections have to be made using general-purpose routing resources, and Reconfigurable Interconnects are used for the purpose of routing.
FIG. 1C shows the multifunction tile by Xilinx according to U.S. Pat. No. 6,573,749. The patent describes the method and apparatus of incorporating a multiplier into an FPGA. The invention provides an alternative structure that shares routing resources with a programmable structure having variable width. The document describes a multifunction tile and in one of the embodiments, the multifunction tile includes a configurable, dual-ported RAM and a multiplier that share the Input/Output resources of the multi-function tile. The RAM block and the multiplier block share their inputs bits and therefore, whenever the multiplier block is being used, the RAM block cannot be used in 32-bit mode.
The connectivity of the multiplier block and RAM block in the above discussed patent is such that whenever the multiplier block is being used, the associated RAM block can only be used in specific modes (18 bits or less). The multiplier inputs and outputs cannot be stored in the associated RAM block.
It is therefore felt that a direct interconnect structure is required between complex IP cores (Digital Signal Processors, Memory, High speed microprocessors) in FPGA, to avoid inefficient performance of general-purpose routing resources and for providing an integral connectivity between the complex IP cores and FPGA.